In FIG. 1 of the drawings, there is shown a known sample-and-hold circuit formed between a high voltage line LH and a low voltage line LL. The known sample-and-hold circuit has a pair of input nodes 1 and 2 which are respectively supplied with a control signal SH1 and the complementary control signal SH2 different in phase from the control signal SH1 by 180 degrees. If the control signal SH1 goes up to a high voltage level VH, the complementary control signal SH2 is shifted from the high voltage level VH to a low voltage level VL. Then, n-p-n type bipolar transistors 3 and 6 turn on to provide conduction paths passing therethrough, however n-p-n type bipolar transistors 4 and 5 are turned off, thereby allowing the sample-and-hold circuit to operate in a sample mode. In the sample mode, when an input signal Sin is applied to an input node 7, an n-p-n type bipolar transistor 8 turns on to serve as an emitter follower, and a series of diodes 9, 10 and 11 serves as a level-shifting circuit for shifting down a voltage level supplied from the output node of a constant current source 12 coupled to the high voltage line LH. Through the n-p-n type bipolar transistor 3 flows the total amount of currents passing through the series of diodes 9, 10 and 11 and the conduction path of the n-p-n bipolar transistor 8, respectively, which in turn flows into a constant current source 13. The current is discharged to the low voltage line LL.
Assuming now that all of the diodes 9, 10 and 11 have respective diode forward voltages (each represented by Vd) approximately equal in value to one another, a voltage level Vb14 at the base node of an n-p-n type bipolar transistor 14 is calculated as follows: EQU Vb14=Vin-Vbe8+3Vd (Eq. 1)
where Vin is the voltage level of the input signal Sin and Vbe8 is the difference voltage or the forwardly biassing voltage between the base node and the emitter node. With the voltage level Vb14, the n-p-n type bipolar transistor 14 turns on to serve as an emitter follower, and a current is supplied from the high voltage line through the n-p-n bipolar transistor 14 to a hold-capacitor 15. Then, the hold-capacitor 15 is charged up to a voltage level Vc15 which is given by Equation 2: EQU Vc15=Vin-(Vbe8+Vbe14)+3Vd (Eq. 2)
where Vbe14 is a forwardly biassing voltage between the base node and the emitter node of the n-p-n type bipolar transistor 14. As will be understood from Equation 2, the voltage level Vc15 at the hold-capacitor 15 follows the voltage level of the input signal Sin but is different from the input signal Vin by the value of (3Vd-Vbe8-Vbe14). The emitter node of the n-p-n type bipolar transistor 14 is coupled to the base node of an n-p-n type bipolar transistor 16 and the emitter node of the n-p-n type bipolar transistor 16 in turn is coupled to an output node 17, so that a voltage level Vout at the output node 17 is calculated as: EQU Vout=Vin-(Vbe8 30 Vbe14+Vbe16)+3Vd (Eq. 3)
where Vbe16 is a forwardly biassing voltage between the base node and the emitter node of the n-p-n bipolar transistor 16. If the n-p-n bipolar transistors 8, 14 and 16 and the diodes 9, 10 and 11 are selected in such a manner as to have respective device characteristics which results in that the sum of the forwardly biassing voltages Vbe8, Vbe14 and Vbe16 is approximately equal to the sum of the respective diode forward voltages of the diodes 9, 10 and 11, it is possible that the voltage level Vout at the output node 17 is approximately equal to the voltage level of the input signal Vin. This means that an output signal Sout appearing at the output node 17 is approximately equal in voltage level to the input signal Sin in the sample mode.
On the other hand, when the control signal SH1 goes down to the low voltage level VL, the complementary control signal SH2 goes up to the high voltage level VH, thereby causing the n-p-n type bipolar transistors 4 and 5 to turn on to provide respective conduction paths. However, with the control signal SH1 of the low voltage level, the n-p-n type bipolar transistors 3 and 6 turn off to block the conduction paths, so that the voltage level at the base node of the n-p-n bipolar transistor 14 is decreased, and, for this reason, the n-p-n bipolar transistor 14 turns off, thereby completing the charging to the hold-capacitor 15. This means that the sample-and-hold circuit is shifted from the sample mode to a hold mode. In the hold mode, the hold-capacitor 15 provides the voltage level Vc15 to the base node of an n-p-n type bipolar transistor 18. The constant current source 12 provides the current through a diode 19 to the n-p-n type bipolar transistors 4 and 5, and the n-p-n type bioplar transistor 18 also provides a current from the high voltage line LH to the n-p-n bipolar transistors 4 and 5. As described hereinbefore, the n-p-n type bipolar transistors 4 and 5 are turned on in the hold mode, the currents provided to the n-p-n type bipolar transistors 4 and 5 flow into the constant current source 13 and a constant current source 20. In this situation, if the voltage level Vc15 is decreased, the n-p-n type bipolar transistor 14 slightly turns on to charge up the hold-capacitor 15. However, if the hold-capacitor 15 is charged up again, the n-p-n type bipolar transistor 14 turns off again. In this manner, the hold-capacitor 15 keeps the voltage level thereof at the constant level determined upon completion of the sample mode. Reference numeral 21 designates a constant current source coupled between the output node 17 and the low voltage line LL. Another sample-and-hold circuit similar in circuit arrangement to that illustrated in FIG. 1 is disclosed by Robert A. Blauschild in "An 8b 50ns Monolithic A/D Converter with Internal S/H", 1983 IEEE International Solid-State Circuit Conference, pages 178 and 179.
However, a problem is encountered in the prior-art sample-and-hold circuits in driftage of the voltage level Vout at the output node 17. Namely, a decay tendency or the droop characteristic takes place in the voltage level Vout at the output node 17. This is because of the fact that the base currents I.sub.B are supplied from the hold-capacitor 15 having a capacitance Ch to the n-p-n type bipolar transistors 18 and 16 coupled to the hold-capacitor 15, which results in that the output signal Sout is gradually decreased in voltage level at a ratio of I.sub.B /Ch. When the sample-and-hold circuit is designed to execute a high-speed operation, the component transistors are enlarged in size to have large current driving capabilities, so that the amount of the base currents I.sub.B are increased. When the base currents I.sub.B are increased, the driftage tendency is also increased in accordance with the above ratio. This results in serious driftage tendency. As a result, the sample-and-hold circuit seems to lose the hold function.
One of the solutions is to replace the bipolar transistors coupled to the hold-capacitor 15 to field effect type transistors so as to decrease the base currents I.sub.B, or alternatively to the transistors with a large current amplification factor, which results in decreasing the base currents I.sub.B without enlargement of the transistor sizes. However, this solution needs to employ additional process dedicated to fabrication of those special transistors, and, for this reason, the fabrication process tends to be complicated. As a result, the solution is not feasible for a sample-and-hold circuit fabricated on a semiconductor substrate.
Another solution is to employ a darlington pair instead of the transistor coupled to the hold-capacitance 15 or to add a current compensation circuit. However, these sample-and-hold circuits can not respond to a high frequency input signal Sin, and, for this reason, the solution is not suitable for a high speed operation.